The present invention relates to semiconductor device and a producing method of a semiconductor device, and more particularly to an accessory pattern structure such as an alignment mark in a semiconductor device and a producing method of an accessory pattern structure.
Description of the Related Art
In recent years, with high integration of LSIs, element areas are reduced year by year, and alignment accuracy improvement is one of important factors in producing a semiconductor device while holding high yield. One factor on which the alignment accuracy largely depends is visibility of an alignment mark, and a good resist form should be thus ensured.
In FIGS. 1 to 4, there is shown a producing method of a conventional alignment mark in a semiconductor device such as a DRAM using a stacked capacitor structure. In FIG. 1, a numeral 1 denotes a semiconductor substrate made of P-type silicon or the like. On a nonactive region of this semiconductor substrate 1, generally, a field oxide film for element separation is formed, and on its active region, for example, a word line made of a first polycrystalline silicon layer and an Nxe2x88x92-type diffusion layer are formed in succession.
Subsequently, a first interlayer insulating film such as a SiO2 layer, a BPSG layer or the like is deposited over the entire surface of the semiconductor substrate 1, and a contact for connecting a bit line made of a second polycrystalline silicon layer and the Nxe2x88x92-type diffusion layer is prepared. Then, the bit line of the second polycrystalline silicon layer is formed. Further, a second interlayer insulating film is deposited so as to cover the entire surface of the semiconductor substrate 1, and thereafter a contact for connecting a storage electrode 3 having a stacked capacitor structure made of a third polycrystalline silicon layer and the Nxe2x88x92-type diffusion layer is formed. The first interlayer insulating film and the second interlayer insulating film, which are deposited before the formation of the storage electrode 3 constitute an interlayer insulating film 2.
Next, the storage electrode 3 having the stacked capacitor structure made of the third polycrystalline silicon layer and a plate electrode 4 made of a fourth polycrystalline silicon layer are formed consecutively, and subsequently a third interlayer insulating film 5 having a relatively thick form is deposited. At this time, the third interlayer insulating film 5 is flattened by, for instance, a conventional CMP (chemical mechanical polishing) technique or the like in order to reduce a step caused between a cell region and a peripheral circuit region by the formation of the storage electrode 3. Moreover, a scribe line region 6 is formed using a conventional photolithographic technique and an etching technique. At this time, the total film thickness formed on the semiconductor substrate 1 is, for example, approximately 2000 nm.
In FIG. 2, a first upper wiring 7 such as W, AL or the like is formed on the third interlayer insulating film 5, and then a metal interlayer film 8a made of, for example, a plasma-SiO2 is deposited to cover the first upper wiring 7. A contact (through hole) for coupling the first upper wiring 7 with a second upper wiring 9 (see FIG. 3) is then formed. Simultaneously, on the scribe line region 6, a ground film 8b made of the metal interlayer film 8a of the plasma-SiO2 is prepared under a region where an alignment mark of the second upper wiring step is formed in the following step.
In FIG. 3, the second upper wiring layer 9 such as W, AL or the like is deposited and a photoresist film 10 is then applied to cover the whole surface.
Finally, in FIG. 4, the photoresist film 10 is patterned using the conventional photolithographic technique to prepare a first resist trace 10a for forming a wiring trace of the second upper wiring 9 within a production region and a second resist trace 10b for forming an alignment mark. At this time, a step or difference in height of approximately 2200 to 2400 nm is produced between the first and the second resist traces 10a and 10b. 
Hence, in the case that the photolithographic technique is used, a focal length of the first resist trace 10a for the wiring trace within the production region is different from that of the second resist trace 10b for the alignment mark. Hence, the resist shape of the second resist trace 10b for forming the alignment mark is extremely degraded, resulting in many problems such as yield drop, and failure to hold the accessory pattern resist such as the alignment mark to cause a pattern separation in etching the second upper wiring 9 and thus yield drop.
Concerning the first problem, when the alignment mark of the second upper wiring step and the accessory pattern are formed, the alignment mark and the accessory pattern are not well prepared to drop the alignment accuracy.
The reason is as follows. That is, with the high integration in the device, the total stacked layers become thick, and a large step or difference in height is caused between the first pattern of the second upper wiring step within the production region and the second pattern such as the alignment mark formed in the lower position than the first pattern. Hence, when the conventional photolithographic technique is used, the two patterns are different in their focal lengths, and it is difficult to prepare the alignment mark and the accessory pattern with high accuracy (having good resist shapes) in the second upper wiring step.
Regarding the second problem, the pattern separation comes off the alignment mark part and the accessory pattern part in the etching step after the formation of the alignment mark of the second upper wiring step and the accessory pattern to cause the yield drop.
The reason is as follows. That is, when the conventional photolithographic technique is used, there is a large height difference between the first pattern of the second upper wiring step within the production region and the second pattern or the alignment mark and the accessory pattern formed in the lower position than the first pattern, and the first and second resist patterns are different in their focal lengths. The resist shape of the accessory pattern such as the alignment mark is extremely made worse, and the resist cannot be held to cause the pattern separation in the etching step.
It is therefore an object of the present invention to provide a semiconductor device in view of the aforementioned problems of the prior art, which is capable of improving alignment accuracy without increasing a nurber of steps, and preventing patterns coming off alignment mark part and the like to avoid yield drop.
It is another object of the present invention to provide a production method of a semiconductor device, which is capable of improving alignment accuracy without increasing a nurber of steps, and preventing patterns coming off alignment mark part and the like to avoid yield drop.
In accordance with one aspect of the present invention, there is provided a semiconductor device comprising a substrate and a projection part for forming an accessory pattern, formed on the substrate.
In accordance with another aspect of the present invention, there is provided a producing method of a semiconductor device, comprising a step for forming a projection part for forming an accessory pattern on a substrate.
In the present invention, the projection part can includes a plurality of insulating layers or a plurality of conductive layers. The plurality of insulating layers or conductive layers of the projection part can correspond to a plurality of insulating layers or conductive layers formed in a pattern part within a production region on the substrate.
In the present invention, the projection part formation step includes steps for forming a plurality of insulating layers or conductive layers. The plurality of insulating layers or conductive layers are left in steps for forming a plurality of insulating layers or conductive layers in a pattern part within a production region on the substrate.
Further, the accessory pattern can include an alignment mark of an upper wiring step.
According to the present invention, the height difference between the wiring pattern and the accessory pattern can be largely reduced. Hence, the alignment accuracy of the upper wiring step can be improved without increasing the number of steps in the conventional process. Further, the pattern separation of the alignment mark and the accessory pattern off the surface can be prevented, and yield drop can be prevented.